1. Field of the Invention
The present invention relates to semiconductor memories, particularly to a semiconductor memory, such as a synchronous dynamic random-access memory (to be referred to as SDRAM hereinafter), using a shift redundancy system and formed by arranging decoding circuits of adjacent select lines (word lines) in a mirror image for the purpose of scale down.
2. Description of the Related Art
To increase the capacity and speed and reduce the consumption power of a memory and to reduce the wiring pitch by scale down, the general approach is to use a hierarchical word line system in a semiconductor memory such as SDRAM. In this hierarchical word line system, word lines are constituted by main select lines (mwl) and sub-select lines (swl). One select line selected by a main decoder (mwldec) is connected to a sub-decoder (swdec) having address information inputs for decoding and the corresponding sub-select line outputs. This sub-decoder selects one sub-select line in accordance with input address information.
For example, when eight sub-select lines belong to one main select line in a hierarchical word line system, to select one of these eight sub-select lines (1/8 selection), the sub-decoder performs 1/8-decoding to select one sub-select line from a main select line selected by the main decoder. For this purpose, eight sub-decoders are prepared for one main select line. Commonly, to reduce the circuit pitch, these eight sub-decoders are divided into two groups. Four sub-decoders are arranged at each end of a cell array block, and four sub-select lines run from these sub-decoders at one end alternately to oppose four corresponding sub-select lines at the other end in an interdigitated pattern.
In this arrangement, to place four sub-decoders within the pitch of eight sub-select lines, some layout improvements are made; four sub-decoders are grouped as one set, and signals and a power supply are shared by two adjacent sets. This is so because the size of a semiconductor integrated circuit is an important factor that determines the size of the whole system, so a reduction of the chip size by sharing is desired. Also, the smaller the chip size is, the larger the number of chips fabricated from one wafer is. Hence, it is essential to reduce the chip size by improving the layout efficiency.
To reduce the chip size in the hierarchical word line system, a method is known by which adjacent decoding circuits or decoding circuit sets are arranged in a mirror image (mirror arrangement or symmetrical arrangement) so that at least some decoding circuits or decoding circuit sets of word lines for selecting memory cells are shared. That is, a sharable portion is formed in a pitch end portion of each decoding circuit or decoding circuit set, and decoders are constituted by turning them back at these sharable portions.
FIGS. 1A and 1B are plan views for explaining the effect of space reduction by the mirror arrangement of decoding circuits. FIG. 1A shows a common shift arrangement, not a mirror arrangement, of adjacent decoding circuits. FIG. 1B shows a mirror arrangement of adjacent decoding circuits.
As shown in FIG. 1B, when two decoding circuits are mirror-arranged, the ground electrode (GND) can be shared by these decoding circuits. This can reduce the space in a direction perpendicular to word lines compared to the shift arrangement as shown in FIG. 1A. In this example, the space of two decoders in the direction perpendicular to word lines is 3.2 .mu.m in the shift arrangement, whereas this space can be reduced to 2.4 .mu.m in the mirror arrangement. That is, a space reduction of 0.8 .mu.m is achieved.
Semiconductor memories such as SDRAMs are mass-produced because of their characteristics as products, and it is necessary strictly to guarantee the quality of each individual product. To guarantee this quality, various tests and evaluations are conducted before the shipment of products. The time required for these tests and evaluations is an important factor for determining the fabrication cost.
In guaranteeing the quality of a semiconductor memory, a shift redundancy system is known as a method of remedying defectives occurring in memory cells or word lines. In this shift redundancy system, the address of a main select line or a sub-select line is shifted one bit to the higher or lower bit position from a defective portion. In this system, address information on a defective location to be subjected to redundancy processing is loaded upon start-up of a device. In accordance with this address information, the relationships between decoders and drivers of select lines are appropriately switched, so that the defective address portion is not selected. Accordingly, no redundancy determination is necessary from the subsequent access, so it is possible to increase the access speed and reduce the consumption power. This address information of a defective portion is previously stored in an internal ROM or the like of a memory. Even if a memory cell or the like has a defect, therefore, by redundancy processing, the memory can be operated normally, without selecting this defective memory cell.
This shift redundancy system will be described below with reference to FIGS. 2 to 4. FIGS. 2 to 4 are enlarged plan views of a cell array portion and a sub-decoder portion. In FIGS. 2 to 4, not only sets of four sub-decoders but also sub-decoders in each set are mirror-arranged. Of an externally input row address, a lower address (3 bits) is used to select a sub-decoder, and an address higher than that is used to select a main decoder.
When the lower bit address is incremented from 0, sub-select lines swl&lt;0&gt; to swl&lt;31&gt; juxtaposed from the upper end to the lower end of FIG. 2 are sequentially selected as indicated by their numbers. Even when the externally given address is sequentially incremented, these select lines are not sequentially selected from the end as shown in FIG. 2. This is so because adjacent sub-decoders are mirror-arranged, so the order of addresses on the device is inconsistent with the order of externally supplied addresses.
Sub-decoders on the right-hand side of the cell array in FIG. 2 are laid out such that sub-decoders 51 to 54 selected by main select line &lt;0&gt; (mwl&lt;0&gt;) and sub-decoders 55 to 58 selected by a main select line &lt;1&gt; (mwl&lt;1&gt;) are mirror-arranged with respect to the boundary between the sub-decoders 54 and 55.
Furthermore, of one set of the sub-decoders 51 to 54 selected by main select line &lt;0&gt; (mwl&lt;0&gt;), the sub-decoders 51 and 52 and the sub-decoders 53 and 54 are mirror-arranged with respect to the boundary between the sub-decoders 52 and 53. Sub-decoders selected by the other main select lines &lt;1&gt; (mwl&lt;1&gt;) to &lt;3&gt; (mwl&lt;3&gt;) are similarly mirror-arranged.
Accordingly, the sub-decoder 58 placed symmetrically with the sub-decoder 51 with respect to the boundary between the sub-decoders 54 and 55 is composed of transistors having the same configuration as the sub-decoder 51 and is selected by the same address signal. This also holds true for pairs of the sub-decoders 52 and 57, 53 and 56, and 54 and 55; these sub-decoders of each pair are symmetrically arranged with respect to the boundary and selected on the basis of the same address signal.
The sub-select lines connected to the sub-decoders located on the right-hand side of FIG. 2 are selected in the order of swl&lt;0&gt;, sw2&lt;2&gt;, swl&lt;4&gt;, and swl&lt;6&gt; by supplying four address signals by selecting main select line &lt;0&gt;. After that, main select line &lt;1&gt; is selected to supply address signals in the same order. As a consequence, these sub-select lines are selected in the order as shown in FIG. 2.
To test and evaluate a semiconductor memory, it is sometimes necessary to select sub-select lines regularly in a certain direction, in order to write data in the form of a specific pattern by a physical image in the storage of a memory cell to check the influence on adjacent memory cells, to check the influence when a memory cell at a specific distance from a memory cell of interest is repeatedly accessed, or to allow easy progress of an analysis when defects have occurred. For this purpose, arithmetic processing is sometimes done for addresses generated by an IC tester to select sequentially these sub-select lines in accordance with their positions.
FIG. 3 shows an example in which arithmetic processing is performed for externally applied addresses. In this example, a lower address of a row address is used as a selection address of a sub-decoder, a higher address of the row address is used as a selection address of a main decoder, and the address is incremented from lower bits. Sub-select lines swl&lt;0&gt; to swl&lt;16&gt; juxtaposed from the upper end to the lower end of FIG. 3 are selected in the order of numbers in parentheses shown in FIG. 3.
As described above, sub-select lines can be sequentially selected in a certain direction by performing predetermined arithmetic processing for addresses generated from an IC tester.
For example, this arithmetic processing performed for addresses generated by an IC tester is as follows:
RA0=A0 XOR A1 PA0 RA1=A1 XOR A2 PA0 RA2=A2 XOR A3 PA0 RA3=A3 PA0 RA4=A4 PA0 . . .
In the above arithmetic processing, A0, A1, . . . , are original addresses generated by an IC tester, and these addresses are incremented. RA0, RA1, . . . , are addresses after the logical operation, which the IC tester actually supplies to the device.
In a memory in which sub-decoders are mirror-arranged as described above, sub-select lines can be sequentially selected in accordance with their physical positions by previously arithmetically processing addresses generated by an IC tester and supplying the obtained addresses to the device. Accordingly, it is readily possible to obtain the correspondence between the sequentially incremented addresses and the actually selected sub-select lines. This allows accurate testing/evaluation of a semiconductor memory.
Unfortunately, when addresses generated by an IC tester are given to a device after being arithmetically processed as shown in FIG. 3, the following problem arises if shift redundancy processing is performed.
As shown in FIG. 4, assume that a defect has occurred in a block of main select line &lt;1&gt; and so main select lines are shifted one bit downward in FIG. 4 in order to perform a defect remedy process. In this case, if an address is incremented by performing the aforementioned arithmetic processing by an IC tester, the order of selection of sub-select lines changes as indicated by the numbers in parentheses of FIG. 4.
Referring to FIG. 4, X marks indicate that sub-select lines belonging to defective main select line &lt;1&gt; are not selected. That is, these select lines are not selected because redundancy processing is performed.
As is apparent from this FIG. 4, in a block of main select line &lt;0&gt; before defective main select line &lt;1&gt;, sub-select lines are selected in order from the uppermost one. However, in blocks of main select lines &lt;2&gt; and &lt;3&gt; after defective main select line &lt;1&gt;, the order of selection of sub-select lines reverses itself. This reverse itself selection occurs because eight sub-decoders selected by main select line &lt;1&gt; are mirror-arranged with respect to eight sub-decoders selected by main select line &lt;2&gt;. That is, when main select line &lt;1&gt; is subjected to redundancy processing, address signals for the sub-decoders belonging to this main select line &lt;1&gt; are directly input to the sub-decoders belonging to main select line &lt;2&gt;. This reverses itself the order of selection of these sub-decoders.
When addresses from an IC tester are given to a device after being arithmetically processed as described above, sub-select lines after defective main select line &lt;1&gt; are no longer sequentially selected in accordance with their physical positions. This makes it difficult to establish the correspondence between the addresses generated by the IC tester and the actually selected sub-select lines. Consequently, it becomes impossible to perform accurate testing/evaluation.
As described above, when the conventional system is used in a semiconductor memory having mirror-arranged sub-decoders, to select sub-select lines in the intended order in testing/evaluation or the like, it is necessary previously to process input addresses arithmetically. Even when the arithmetically processed addresses are input, sub-select lines cannot be selected in a predetermined order if defect remedy is performed by shift redundancy processing.
The following means must be used to prevent this selection order change due to the presence/absence of redundancy.
The presence/absence of redundancy or a bit subjected to redundancy processing changes in accordance with the presence/absence of a defect or the location of a defect in each chip. To control all possible cases in the stage of testing/evaluation, address logical arithmetic expressions to be selected in accordance with the location of a defect are prepared and: (a) address information of a bit subjected to redundancy processing is checked whenever testing/evaluation is performed, and an appropriate address logical arithmetic expression corresponding to the address information is chosen; or (b) information on a defective address used when redundancy processing is performed is stored, and this information is extracted to select an appropriate address logical arithmetic expression and start testing/evaluation.
In the above method (a), however, it is necessary to recheck the defect address, and this requires a long testing/evaluation time. As a consequence, the testing/evaluation cost rises. In the method (b), defect address information of each device must be stored in a certain storage device, resulting in an increase in the cost of hardware resources. An enormous cost rise results when the number of devices to be processed increases.
Furthermore, in both methods (a) and (b), it is necessary to prepare logical arithmetic expressions for address conversion for all possible combinations and define proper correspondence between defect addresses and these logical arithmetic expressions. This requires very cumbersome work. Also, actual redundancy processing requires troublesome processing, e.g., selecting an appropriate logical arithmetic expression by referring to the contents of the aforementioned definition.